The present invention relates to an improvement in a bipolar semiconductor device, and a method of manufacturing the same.
A selective epitaxial technique, which provides a high-speed bipolar semiconductor device, has recently been attracting attention. The selective epitaxial technique is described in, e.g., N. Ohuchi et al., "A New Self-Aligned Transistor Structure for High-Speed and Low-Power Bipolar LSIs", IEDM Tech. Dig., pp. 55-58, 1983.
A method of manufacturing a bipolar transistor using the selective epitaxial technique will be described with reference to FIG. 1. N.sup.+ -type buried layer 2 is formed in the surface of p-type silicon substrate 1. CVD oxide film 3 is formed on the entire surface of the resultant structure. Film 3 is selectively etched to form openings 13 and 14. N-type monocrystalline silicon layers are formed in openings 13 and 14 by selective epitaxy. The upper surfaces of the n-type monocrystalline silicon layers are recessed to correspond to the forms of openings 13 and 14. During formation of the n-type monocrystalline silicon layers, a polycrystalline silicon layer is formed on film 3. An n-type impurity is selectively ion-implanted in the monocrystalline silicon layer formed in opening 13 to form n.sup.+ -type collector connection region 5. A thermal oxide film is formed on the surfaces of the monocrystalline silicon layers and the polycrystalline silicon layer on film 3. A silicon nitride film is then formed on the thermal oxide film. Photoresist is applied to the entire surface of the resultant structure, which is then etched by reactive ion etching. Thus, the thermal oxide film, the silicon nitride film and the photoresist are left only on the recessed portion of layer 4. Etching back of this type is described in S. Shibata et al., "A Simplified BOX (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories", IEDM Tech. Dig., pp. 27-30, 1983.
Boron is ion-implanted in the n-type epitaxial layer in opening 14 and in the polycrystalline silicon layer on film 3 in the vicinity of the n-type epitaxial layer to form p-type graft base 6. The polycrystalline silicon layer on film 3 is etched so that a prospective base-emitter region (near the second opening) and a prospective collector connection region (near the first opening) are electrically isolated.
Annealing is performed to activate impurities in regions 5 and 6. Selective oxidation is then performed by using as a mask the remaining silicon nitride film, thus forming thermal oxide film 7. The silicon nitride film and the underlying thermal oxide film are removed. Emitter, base, and collector electrodes 10, 11, and 12 are thus formed.
When the above selective epitaxial technique is used to manufacture a bipolar transistor, the base region of the transistor can be made small, thereby decreasing base resistance. As a result, transistors manufactured with the above method are capable of high-speed and high-frequency operation.
In transistors capable of high-speed operation, an impurity must be doped at a high concentration in region 5. This is to decrease the resistance of region 5, thereby reducing the overall collector-series resistance of the transistor.
In the above method, it is preferable that annealing for forming region 5 be performed at as low a temperature as possible to maintain a high emitter-collector breakdown voltage. To form region 5 having a high impurity concentration and reaching layer 2, annealing must be performed at a temperature of about 1,000.degree. to 1,100.degree. C. for several to tens of minutes. When such high-temperature annealing is performed, however, the impurity is diffused from layer 2 and redistributed, thereby decreasing the emitter-collector breakdown voltage of the transistor.
Region 5 as mentioned above is formed with the following steps: (1) a monocrystalline silicon layer is formed by selective epitaxy; (2) an n-type impurity is selectively ion-implanted in the monocrystalline silicon layer; (3) part of the polycrystalline silicon layer on film 3 is removed; (4) the monocrystalline and polycrystalline silicon layers are patterned (to be isolated); and (5) the resultant structure is annealed. These steps are necessary because an impurity is diffused at a considerably high rate in the polycrystalline silicon layer formed on film 3. Therefore, when annealing is performed, n-type impurity may be diffused in the base region. The polycrystalline silicon layer is removed to prevent this. However, the above-mentioned steps (1) to (5) are complex in procedures, and productivity suffers.